Clock Skew Compensation Algorithm Immune to Floating-Point Precision Loss

Reduced-Precision Floating-Point Analysis

Adaptive Precision Floating Point LLL

The LLL algorithm is one of the most studied lattice basis reduction algorithms in the literature. Among all of its variants, the floating point version, also known as L, is the most popular one, due to its efficiency and its practicality. In its classic setting, the floating point precision is a fixed value, determined by the dimension of the input basis at the initiation of the algorithm. We ...

Automated Floating-Point Precision Analysis

Title of dissertation: Automated Floating-Point Precision Analysis Michael O. Lam, Doctor of Philosophy, 2014 Dissertation directed by: Professor Jeffrey K. Hollingsworth Department of Computer Science As scientific computation continues to scale upward, correct and efficient use of floating-point arithmetic is crucially important. Users of floating-point arithmetic encounter many problems, inc...

A Single Precision Asynchronous Floating Point Multiplier

This paper presents the delay of carry save based multiplier of 65nm technology using Field Programmable Gate Array is in enable mode. Here we present a design of floating point multiplication and that can utilize the decimal carry save addition is reduce path delay and dissipation power. The multiplier can stores a less number of multiplicand uses a decimal carry save addition in the portion o...

A dual precision IEEE floating-point multiplier

We present a design of an IEEE oating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. In single-precision the la-tency is two clock cycles and in double-precision the latency is three clock cycles, where each pipeline stage contains roughly fteen logic levels. A single-precision multiplication can be followed immediately by a...